Single-Event Effects

The Physics of SEEs

When a high-energy ion (from galactic cosmic rays, solar protons, or trapped radiation) passes through a semiconductor, it leaves behind a track of ionization. The energy loss along this track is described by Linear Energy Transfer (LET), measured in MeV·cm²/mg.

If the deposited charge within a transistor’s sensitive volume exceeds the critical charge (Qcrit) needed to change its state, an SEE occurs.

• In logic or memory, this may simply flip a bit.

• In power devices, the same energy deposition can trigger catastrophic events like latchup or burnout.

Advanced technology nodes (deep submicron CMOS) are more vulnerable because their Qcrit is smaller—fewer charges are needed to induce an error.

Single-Event Upset (SEU) — The Bit Flip

An SEU is the most common SEE: a change of state in a memory cell or logic element.

• In static RAM, a bit may flip from “0” to “1” when a particle injects charge into the storage node.

• In digital logic, transient glitches may propagate as incorrect instructions or data.

SEUs are non-destructive—the device can be reset or corrected. But if left unchecked, they can corrupt data or cause unintended behavior. For example, an SEU in a spacecraft’s control register may issue spurious commands.

Mitigation: Error-correcting codes (ECC), triple modular redundancy (TMR), scrubbing memory periodically, and watchdog resets. Shielding reduces SEU rates for protons, but heavy ions remain difficult to block.

Single-Event Latchup (SEL) — Runaway Currents

SEL occurs when a particle strike triggers a parasitic thyristor structure inside CMOS devices, creating a low-impedance path between power and ground. This drives sustained high currents until the device is powered off or fails.

Latchup can cause permanent damage if not corrected quickly, especially in power devices. Modern CMOS geometries and higher integration density make latchup a significant concern.

Mitigation: Current limiting circuits, power cycling systems, rad-hard device processes (silicon-on-insulator, guard rings), and localized spot shielding.

Single-Event Burnout (SEB) — Catastrophic Failure in Power Devices

SEB is a permanent, destructive failure in power transistors (e.g., MOSFETs, IGBTs) when a particle strike induces avalanche breakdown. The localized heating and runaway current destroy the device, rendering it unusable.

Because SEB is catastrophic, spacecraft systems that experience it cannot recover without redundancy. SEB is a major driver in choosing radiation-hardened power components for critical subsystems.

Mitigation: Use of rad-hard power devices, derating voltages to below breakdown thresholds, and enclosure shielding to reduce proton and ion fluxes.

Single-Event Gate Rupture (SEGR) — Breakdown of Gate Oxides

SEGR occurs when a particle strike in a high-field region causes a localized breakdown of a transistor’s thin gate oxide. This punctures the oxide permanently, creating a conductive short between gate and channel.

Like SEB, SEGR is destructive and unrecoverable. It is most common in power MOSFETs and high-voltage devices.

Mitigation: Rad-hard processes with thicker oxides, voltage derating, and the use of alternative transistor designs (e.g., SiC or GaN devices, which show different SEE responses).

How SEEs Are Measured and Modeled

• Cross Section (σ): SEE susceptibility is quantified as a cross section (cm²/device), measured by irradiating devices with beams of heavy ions or protons at accelerators.

• LET Threshold: The minimum LET value at which upsets occur is determined experimentally.

• Rate Predictions: Models such as CREME96 or OMERE combine orbital particle fluxes with device cross sections to estimate SEE rates in a given orbit.

For example, a CubeSat in LEO may experience one SEU per day in unprotected SRAM, while a GEO satellite might see higher SEU rates due to trapped electrons and cosmic ray interactions.

SEEs in Historical Missions

• Galaxy IV (1998): Failure attributed to an SEE in the satellite’s control processor, causing a $250M loss and widespread pager network outages.

• Telstar-401 (1997): Knocked out by a solar storm, where high-energy protons drove SEE-related anomalies that cascaded into permanent failure.

• ISS onboard computers: Regularly experience SEUs in memory, corrected by scrubbing and redundancy protocols.

These cases demonstrate that SEEs are not hypothetical—they have shaped mission outcomes and driven design standards across the industry.

Mitigation Strategies: A Layered Defense

Because SEEs are stochastic, no single solution suffices. Engineers apply layered defenses:

1. Shielding: Reduces proton fluxes and TID, lowering SEE rates in some environments.

1. Rad-hard Design: Devices fabricated with SOI or enclosed layout transistors resist latchup and burnout.

1. System Architecture: ECC, TMR, and watchdog timers catch and correct SEUs in real time.

1. Redundancy: Multiple processors or parallel boards ensure a single SEE does not end the mission.

This layered strategy recognizes that SEEs cannot be eliminated, only managed to tolerable levels.

Why SEEs Matter for Future Missions

As electronics scale down and missions increasingly rely on COTS processors for high-performance tasks (AI, image processing, data handling), SEEs become more pressing. Smaller geometries reduce Qcrit, making devices more upset-prone, while lower voltages reduce margins for error.

Future spacecraft will need to embrace hybrid solutions: advanced composites for spot shielding, rad-hard controllers for critical systems, and fault-tolerant architectures to allow COTS devices to survive despite high SEE rates.